Research on high linearity analog counter for digital pixel circuit

The analog counter counts the input pulses by increasing the analog voltage. The input pulse controls the charging and discharging process of the counting capacitor to increase the voltage on the capacitor, and the voltage value is proportional to the number of pulses. There are two main design methods for analog counter: one is to charge the capacitor through a current source within a certain period of time, and the voltage on the capacitor increases during each high-level pulse; The second is the redistribution of charge between two capacitors, transferring the charge on the small capacitor to the large capacitor, achieving a voltage increase on the large capacitor. This paper simulates and analyzes three analog counter Structures implemented by the above two methods, comparing their performance in terms of counting step consistency, area, swing, DNL (Differential Non-linearity), and INL (Integral Non-linearity). Based on the above analysis, an analog counter with high linearity and high swing is designed in 180nm standard CMOS process, with a resolution of 7 bits and a swing of 0.4V~3.3V. In the worst case, the DNL is 0.039LSB and the INL is 0.206LSB. Compared with a digital counter of the same resolution, the proposed analog counter significantly reduces the layout area occupied. Compared with previous designs, the proposed analog counter circuit with its advantages of small area and low power consumption, can be applied to infrared focal plane digital pixel circuit.