Voltage-Controlled Ring Oscillator with Reliability Criterion for Radiation Effects

This paper presents the technical implementation characteristics of a Voltage Controlled Ring Oscillator (VCRO) with ring architecture using Single Event Effects (SEE) mitigation techniques. By applying the Cadence Virtuoso Analog Design Environment (ADE), the project was implemented at layout level using CMOS UMC 0.18 µm technology based on closed geometry components in accordance with the DARE (Design Against Radiation Effects) standard. Results obtained through simulation indicate current = 14mA, phase noise (PN@1M) = -83.37 dBc/Hz and area = 12.52 µm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.