LC-VCO with 1.6 GHz Tuning Range and Switched Cross-Coupled Core for Power Optimizing

A novel LC-VCO topology derivation is proposed is this work, considering a set of structures for performance enhancement: a Switched Varactors Array (SVA) is applied for discrete frequency control with extended tuning range, a Switched Cross-Coupled Core (SCC) mechanism is proposed for defining the proper power level for each frequency subrange and a degeneration resistor core-based topology is adopted for phase noise performance enhancement. From schematic level design in Cadence environment (TSMC 65 nm CMOS technology), design conditions include V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</inf> = 1.2 V and bias current I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</inf> = 2.47 to 10.3 mA, and performance parameters indicate phase noise PN@1MHz = -127 to -131 dBc/Hz and tuning range FTR = 91% (FoM<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> = -210).

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Published
2024-10-14
DOI
https://doi.org/10.1109/dttis62212.2024.10780219
Primary Topic
Radio Frequency Integrated Circuit Design
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article
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article

LC-VCO with 1.6 GHz Tuning Range and Switched Cross-Coupled Core for Power Optimizing

Leandro Tiago Manera, Agord M. Pinto, Roberto Lacerda de Orio, Eduardo Rodrigues de Lima et al.
Radio Frequency Integrated Circuit Design
article

LC-VCO with 1.6 GHz Tuning Range and Switched Cross-Coupled Core for Power Optimizing

Leandro Tiago Manera, Agord M. Pinto, Roberto Lacerda de Orio, Eduardo Rodrigues de Lima, Raphael R. N. Souza
article en

Abstract

A novel LC-VCO topology derivation is proposed is this work, considering a set of structures for performance enhancement: a Switched Varactors Array (SVA) is applied for discrete frequency control with extended tuning range, a Switched Cross-Coupled Core (SCC) mechanism is proposed for defining the proper power level for each frequency subrange and a degeneration resistor core-based topology is adopted for phase noise performance enhancement. From schematic level design in Cadence environment (TSMC 65 nm CMOS technology), design conditions include V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</inf> = 1.2 V and bias current I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</inf> = 2.47 to 10.3 mA, and performance parameters indicate phase noise PN@1MHz = -127 to -131 dBc/Hz and tuning range FTR = 91% (FoM<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> = -210).

TU Wien (AT), Universidade Estadual de Campinas (UNICAMP) (BR)
Affordable and clean energy
Openalex Percentile: Top 79%
Radio Frequency Integrated Circuit Design
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LC-VCO with 1.6 GHz Tuning Range and Switched Cross-Coupled Core for Power Optimizing — Leandro Tiago Manera, Agord M. Pinto, et al. · (2024) | TGRS Research Map | TGRS