How Systolic Array Dataflow impacts on the resilience to hardware faults

In the recent years, Deep Learing (DL) algorithms became so accurate that started to surpass human performance in a wide range of tasks and are now currently used in applications that would be considered science-fiction only 10 years ago. However, everything has a cost and, for DL, it corresponds to the high-demands requirements in terms of computational power that drove the development of specialized hardware architectures (i.e., hardware accelerator) for DL workloads. One of the most popular hardware accelerator is the Systolic Array (SA) architecture, which is suitable to run inferences with low energy, low latency and high throughput. In particular, there exist virtually infinite types of SA in terms of dataflow depending on the kernel they have to run. If from one hand SA dataflow has been widely studied to improve energy efficiency and performance, the impact on the resilience to hardware faults has been neglected. Hardware faults can indeed jeopardize the execution of DL kernels leading to miss-classification and eventually to dramatic impacts when DL are used in safety-critical applications, such as autonomous driving. In this paper, we study how hardware faults are propagated through the SA depending on the dataflow and how the inference is impacted.