Power Consumption Reduction in Integrated Pacemakers: Design Strategies for Cortex-M0+ Processors

For medical implantable devices such as pacemakers, minimizing power consumption is crucial to ensure long-lasting and reliable operation. In this context, this paper explores the design of integrated Cortex-M0+-based processors integrated into pacemakers with a focus on reducing power consumption. Indeed, the processor is the part of the pacemaker that consumes most of the battery energy due to its various operation modes. Key factors influencing its static and dynamic power consumption, including the choice of the right CMOS technology, are analysed and discussed. An approach to reduce the power consumption of the Cortex-M0+ processor is investigated involving an adjustment of the transistor geometric parameters of the standard cell libraries. Considering the TSMC65 65 nm technology, a notable 17.2 % reduction in the total power consumption of the Cortex-M0+ has been obtained while maintaining a maximum operating frequency of 100 MHz, thus highlighting a promising advancement in enhancing the energy efficiency of pacemaker systems.