A 6-bit Low-Area Hybrid ADC Design For System-on-Chip Measurements

In recent years, with the declining dimensions of transistors, the system-on-chips (SoCs) have had more physical defects. These physical defects ultimately result in failures that cannot be tolerated in functional safety applications such as electric cars, aerospace, etc. For the digital peripherals of the SoCs, there are well-known methods such as scan chains, whereas there are methods for analog circuits such as analog scan chains or Analog Test Bus (ATB).This paper presents a 6-bit, low-area Analog-to-Digital Converter (ADC) for SoC analog voltage measurements. The advantage of the proposed ADC design is the low additional area cost to the design of the SoC and increasing the testability of the analog peripherals. This ADC design converts the analog signals, which are difficult to observe, to the digital domain, which is easy to route and observe. This architecture comprises two small ADCs for doing coarse and fine conversions. The ADC for the coarse conversion is a 3-bit SAR ADC, and the ADC for the fine conversion is a 3-bit flash ADC. The suggested ADC is implemented using the 130 nm technology of the Infineon, and it has a total area of 0.007 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The fine ADC of the proposed ADC can be shared between the peripherals nearby inside the SoC, and the additional area per peripheral would be only 0.0015 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The Signal-to-Noise Distortion Ratio (SNDR) of the design is 37dB, and the Figure of Merit (FoM) is 2.15 pJ/conv.