Selectively Self‐Aligned Sol‐Gel Copper Oxide for Large‐Area Multi‐Valued Logic Devices

Rapid expansion of digital information density has led to a growing demand for multi-valued logic (MVL) systems, which aim to minimize energy and time consumption for computations. Heterojunction transistors represent a class of device architectures for MVL circuits; however, partially layered structures can be realized only for vacuum-deposited organic and transferred 2D materials due to the constraints of patterning processes. In this study, a novel Cu_xO/IGZO heterojunction-based ternary inverter is presented via a sol-gel technique and direct patterning process using a self-assembled monolayer (SAM). This approach allows for a promising alternative to conventional photolithography, with the electrical characteristics of SAM-processed oxide thin-film transistors closely matching those of pristine devices. Structural investigations validate the partially overlapped heterojunction and its smoothness. Depth profiling with x-ray photoelectronspectroscopy highlights an oxidation gradient in Cu_xO, suggesting enhanced hole introduction at the IGZO interface. This mechanism potentially supports efficient hole transport and negative differential transconductance, foundational for MVL systems. Such advancements signify the potential for solution-processable digital electronics that offer streamlined fabrication at an affordable budget.