Chiplet Placement Based on Simulated Annealing with Multi-Precision Thermal Simulation

With the advent of the post-Moore era, chiplet gains more and more attention. Due to the compact package of multi-chip system, it is necessary to perform chip let placement with consideration of thermal optimization. To alleviate the problem of heavy complexity, the idea of multi- precision simulation is introduced, and we propose a thermal placement algorithm based on simulated annealing algorithm with assistance of multi-precision thermal simulation. Numerical results demonstrate that it can reduce the peak operating temperature of the whole chip let-based system while optimizing the total wirelength. Furthermore, the significant reduction of running time suggests its potential application in the agile development of multi-chip system.