A Depletion-enhanced N Layers Stacked LDMOS

With the development of power integrated circuits, LDMOS devices assume a significant role in power device applications due to their elevated input impedance and enhanced conversion rate. Nonetheless, a contradictory relationship exists between the breakdown voltage and specific on-resistance in power LDMOS devices. Consequently, an n-layer stacked lateral double-diffused metal-oxide-semi conductor transistor(SLDMOS) is proposed, in which numerous MOS cells are stacked under the same chip area. The on-state resistance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{R}_{\mathrm{o}\mathrm{n}})$</tex> of the n layers S-LDMOS is decreased significantly because of the vertical parallel connection, also the interference among devices is weakened through electrode interconnection isolated by oxidation layer. Multiple drift regions are formed by alternate epitaxy N-layer (drift region) and P-layer (substrate), and each drift region is depleted by the top and bottom P substrates, leading to a much lower <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{R}_{\mathrm{o}\mathrm{n}}$</tex>. The lightly-doped substrate and N/P top region are used to improve the breakdown characteristics, and the floating P layers are introduced to enhance the depletion effect in drift regions and decrease device thicknesses. By optimizing the configuration, a balanced trade-off is obtained. The simulation results indicate that compared with the traditional LDMOS, the 2 layers S-LDMOS exhibits a BV of 356 V and a specific on resistance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{R}_{\mathrm{o}\mathrm{n},\mathrm{s}\mathrm{p}})$</tex> of 13.56 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{\mathrm{m}\Omega\cdot \text{cm}^{2},}$</tex> an improvement of 26.2 % and 71.6%, respectively. And the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{R}_{\mathrm{o}\mathrm{n}}$</tex>, sp of n layers S-LDMOS will be reduced to less than 1/n of C-LDMOS further.