A Design Method to Enhance the Short-Circuit ability of Planar Gate SiC MOSFET

This paper proposes a novel design method to enhance the short-circuit endurance of planar gate SiC MOSFET, investigated by the numerical simulation. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{N}+$</tex> source regions were placed intermittently in the orthogonal direction rather than a conventional stripe pattern source region, which reduces the average temperature of the unit cell and the saturation drain current (IDS,sat) during short-circuit event, avoiding thermal concentration effects, and thus preventing burnout. Compared to conventional SiC MOSFET that increase length of channel (Lch=0.8um) to improve short-circuit endurance, device simulation results show that the maximum saturation drain current under the short-circuit event of 800 V DC bus voltage of the proposed device is reduced by about 11.4%, the threshold voltage (Vth) is largely unperturbed, and the lower specific on-resistance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\boldsymbol{(\mathrm{R}_{\mathrm{o}\mathrm{n},\mathrm{s}\mathrm{p}})}$</tex> is reduced by about 5%. Additionally, it has been demonstrated that reducing the proportion of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{N}+$</tex> source region <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\gamma)$</tex>, within a certain range does not deteriorate the forward conduction voltage drop.