A New 8T SRAM Cell Design of Low-Power and High-Write-Speed

In this paper, a low-power 8T cell structure with high writing ability is proposed. The proposed SRAM basic cell circuit eliminates the write-1 issue by adding two PMOS transistors, resulting in a faster write speed for the cell structure. This design achieves a larger write margin without the need for additional circuits. The results show that, compared to other SRAM cells, the proposed SRAM cell has satisfactory performance in terms of power consumption, write margin, and read access time.