MSANet: Congestion Prediction for Chip Routing Based on Multi-Scale Attention Network

Placement and routing are the most time-consuming parts of the chip design process. Reducing routing congestion is crucial for optimizing placement and improving routability. However, existing congestion prediction models cannot fully utilize the feature information of the chip placement during the prediction process, leading to low prediction accuracy. Therefore, this paper proposes a new multi-scale perception convolutional neural network, called MSAN et, to extract and fully utilize the rich multi-scale feature information from chip placement diagrams, thereby improving the accuracy of predicting routing congestion hotspots. To sufficiently demonstrate the prediction ability of the proposed MSAN et, we conduct extensive experimental validation on two publicly classical datasets. The experimental results show that MSAN et achieves a 46.5% improvement over the existing state-of-the-art methods on the ISPD2015 benchmark dataset, which demonstrates the strong effectiveness of the proposed multi-scale attention mechanisms and shortcut operations of the MSAN et. Moreover, on the large-scale CircuitN et dataset, our MSAN et achieve a 7.1 % improvement compared to the original model, demonstrated the superiority of our approach.