Study on the Characteristics of 3.5kV Buried FS Layer Pulse Thyristor

Pulse thyristors have found wide applications in the field of pulsed power technology due to their high peak current and high voltage withstand capabilities. However, traditional round pulse thyristors are constrained by process conditions. During turn-on, the relatively slow two-dimensional expansion speed of carriers can lead to local overheating and subsequent device failure under high di/dt conditions due to current concentration. Additionally, specific application scenarios require pulse thyristors to possess a certain level of reverse voltage withstand capability. This paper proposes a square pulse thyristor with an embedded FS layer and conducts simulation studies on key parameters affecting device characteristics. The results indicate that increasing the cathode width <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{W}_{\mathrm{N}^{+}}$</tex> and cell width <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{W}_{\text{cell}}$</tex> is beneficial for reducing the on-state voltage drop, and increasing <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{W}_{\mathrm{N}^{+}}$</tex> is conducive to enhancing the peak current. However, excessively large <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{W}_{\mathrm{N}^{+}}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{W}_{\text{cell}}$</tex> can result in uneven current distribution beneath the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{N}^{+}$</tex> cathode region. Reducing the subsurface concentration <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{N}_{\mathrm{N}}{ }^{+}{}_{-}\text{Pbase}$</tex> in the P-base region aids in decreasing the on-state voltage drop, but excessively low <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{N}_{\mathrm{N}}{ }^{+}{}_{-}\text{Pbase}$</tex> can adversely affect the device's forward voltage withstand capability. The concentration of the FS layer (NFS), the thickness of the N2-base region <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{d}_{\mathrm{N}2^{-}})$</tex>, and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{N}_{\mathrm{N}}{ }^{+}{}_{-}\text{Pbase}$</tex> all positively correlate with the device's turn-on delay time. The minority carrier lifetime influences the device's blocking characteristics, conduction characteristics, and pulsed discharge characteristics, with a positive correlation observed. In practical processes, gettering techniques can be employed to maximize the minority carrier lifetime, thereby ensuring optimal device characteristics.