Research on Hardware Acceleration Technique for Weight-Based Fixed Pulsed Arrays

In recent years, with the rapid development of deep neural networks, their model size and computational volume are getting larger and larger, and there are often problems such as power consumption and latency when they are used in embedded applications. To address these problems, ping-pong operation, data fixed-point quantization, and weight-fixed pulsed array hardware acceleration methods are proposed to solve these problems. In this paper, the LeNet-5 model algorithm is taken as an example for hardware acceleration design implementation. Finally, the performance is evaluated by performing on a heterogeneous Xilinx Zynq-7000 platform. The results from the experiment demonstrate a notable 20-fold boost in speed achieved by the custom accelerator outlined in this study when compared to the performance of a CPU. Additionally, in terms of energy efficiency, the custom accelerator significantly outperforms both the CPU by 1.3 times and the GPU by an impressive 26-fold margin.