A Fast Transient Response Capacitor-Less LDO with Dual Transient Enhancement

This paper proposes a capacitor-less LDO with fast transient response. A dual-regulated transient enhancement circuit is proposed, which includes an undershoot suppression circuit and an overshoot suppression circuit. The circuit detects changes in the LDO output voltage (dvout/dt) and converts the voltage change into a current that charges or discharges the power transistor gate and the LDO output directly without going through the error amplifier loop. Using a unipolar folded cascade operational amplifier to achieve high gain while simplifying the distribution of zeros and poles in the LDO loop. A dual cascade compensation structure is used to ensure that the LDO loop has sufficient phase margin under both heavy and light load conditions. At the same time, the compensation structure also provides a fast path from the LDO output to the power transistor gate. The dual-regulated transient enhancement circuit and dual-cascade compensation work together to suppress the overshoot and undershoot of the LDO output voltage caused by load current jumps, improving the transient response of the LDO. The simulation results show that when the load current changes from ImA to 50mA within <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1\mu\mathrm{s}$</tex>, the undershoot of the LDO output voltage is 21m V and the recovery time is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.12\mu\mathrm{s}$</tex> ‘. When the load current changes from 50mA to ImA within <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1\mu\mathrm{s}$</tex>, “the overshoot of the LDO output voltage is 12m V and the recovery time is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.10\mu\mathrm{s}$</tex> ‘.