Shallow Trench Design for Silicon Carbide Planar-Gate MOSFETs

To achieve efficient utilization of power devices, reducing on-resistance and enhancing switching characteristics have always been key research focuses in the field of power devices. Currently, shrinking the cell size of planar MOSFETs is no longer effective in significantly reducing on-resistance, while trench MOSFETs, although they lower the specific on-resistance, introduce reliability issues. This paper investigates the traditional planar SiC MOSFET structure by etching a portion of the JFET region to form a shallow trench-planar MOSFET(STP-MOS), which aims to reduce the device's characteristic on-resistance. The static characteristics of the STP-MOS are analyzed through simulations to determine the impact of different trench depths and widths. A comparison is made between the static and dynamic characteristics of the planar-gate MOSFET and the STP-MOS. According to the results, the reverse breakdown voltage of the STP-MOS is increased by 0.3% compared to the planar-gate MOSFET, while the characteristic on-resistance of the STP-MOS is reduced by 10.17% under the same structural parameters. The gate-drain capacitance (CGD) of the STP-MOS is decreased by 28.57% compared to the planar-gate MOSFET.