On the Design of an Inference Circuit for Tiny Machine Learning

This work explores the development of a hardware accelerator for inference in tiny-scale machine learning applications, with focus on image classification. Through the examination of Artificial Neural Networks (ANNs), the paper details the implementation of a system that incorporates techniques to decrease area and delays mainly in the multipliers and adders. The objective is to achieve an efficient solution in terms of memory amount and energy consumption, while maintaining the accuracy and efficiency of the model. A digital circuit is designed in CMOS 65nm technology. It occupies an area of 0.19 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including the IO structures, a serial interface, a block of memory and the neuron logic. The circuit supports the calculation of one neuron of 64 inputs per clock cycle and the memory contains the configuration of up to 32 neurons organized in one or several layers. Preliminary measurements confirm the correct functioning of the circuit and allow to visualize the next steps towards the application of tiny neural networks.