Study on the Breakdown Characteristics of SiC LDMOS with P-Upper Region

The junction terminal structure is extensively utilized in power electronics due to its substantial ability to enhance breakdown voltage. In this study, utilizing Silvaco TCAD semiconductor device simulation software, we optimally design a SiC LDMOS device incorporating a P-upper region. Initially, the simulation structure of the device is presented. Subsequently, we explore the impact of various parameters, including the spacing between the left side of the P-upper region and the P-body region, the spacing between the right side of the P-upper region and the drain region, the junction depth of the P-upper region, and the doping concentration, on the device's voltage resistance characteristics. Furthermore, the breakdown mechanism is analyzed in terms of surface electric fields, longitudinal electric fields, and peak electric fields. The results indicate that, with a constant doping concentration in the drift region, the breakdown voltage initially decreases and then increases with the reduction of the right-side spacing, while the breakdown voltage on the left-side spacing exhibits a linear relationship. When the left-right spacing is fixed, the breakdown voltage first decreases and then increases with the increase of P-upper junction depth and doping concentration. Comparing these results, it is evident that the optimized P-upper structure in the SiC LDMOS device achieves a more uniform surface electric field distribution, leading to enhanced device reliability and stability.