A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm <sup>2</sup> Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture
A double-pumped 1-read and 1-write pseudo-2-port 6T static random access memory (SRAM) with folded bitline (BL) multi-bank (MB) architecture is demonstrated on 3 nm FinFET technology. A new self-timed clock generator is proposed to optimize wordline (WL) negating with shortcut path circuit (WLNS). sense-amplifier-enable interlocking (SAEI) circuit and the clock generator can provide a 3.6% increase in the maximum operating frequency (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\text {MAX}}$ </tex-math></inline-formula>) by minimizing the tail period of the read operation. The data pre-loading write driver (PLWD) circuit facilitates a shorter separation time between read and write operations by overlapping BL pre-charge and write data loading on the BL, thereby leading to a 4.4% improvement in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\text {MAX}}$ </tex-math></inline-formula>. The WLNS and PLWD contribute to 2.4% <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\text {MAX}}$ </tex-math></inline-formula> gain by promoting contention-free features between the BL pre-charge and write driver circuits. Furthermore, the real-time dynamic performance scaling (RTDPS) feature ensures a robust SRAM read/write operation across the entire supply voltage range by optimizing WL pulsewidth. The test chip measurement results show that it achieves a 5.9% increase in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\text {MAX}}$ </tex-math></inline-formula> at high voltage ranges. In addition, the memory density is 21.1 Mb/mm2, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\text {MAX}}$ </tex-math></inline-formula> is 4.3 GHz, resulting in a figure of merit (FoM) of 90.7 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> Mb/mm2/V.
Authors
- Masaru Haraguchi
- Yoshisato Yokoyama (ORCID: https://orcid.org/0000-0001-8552-4070)
- Koji Nii (ORCID: https://orcid.org/0000-0002-9986-5308)
- Ming‐Hung Chang (ORCID: https://orcid.org/0009-0003-8319-3927)
- Yuxiao Wang (ORCID: https://orcid.org/0009-0004-9454-5972)
- Yorinobu Fujino
- Hong-Chen Cheng
- Yu-Hao Hsu (ORCID: https://orcid.org/0000-0002-3165-1960)
- Tsung-Yung Jonathan Chang (ORCID: https://orcid.org/0009-0007-6505-5474)
Institutions
- Taiwan Semiconductor Manufacturing Company (United States) (US)
- Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
Publication Details
- Journal
- IEEE Journal of Solid-State Circuits
- Published
- 2024-12-12
- DOI
- https://doi.org/10.1109/jssc.2024.3509958
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00