Design and simulation of a DMA controller for FCoE transmission interface

To achieve high-speed performance of Fiber Channel over Ethernet (FCoE) transmission interface, a Direct Memory Access (DMA) controller based on FPGA is designed. The controller supports AXI4 bus protocol and takes Round- Robin strategy for priority arbitration of multi-channel selection (32 channels with eight priorities at maximum). In order to promote the transmission rates of discrete data, the controller supports Scatter/Gather mode based on list descriptors that are stored and analyzed by DMA controller other than the MPU. Therefore, the MPU’s efficiency can be promoted. Using ISim tool of Xilinx ISE development kit, the reading and writing function of the DMA controller is verified through BRAM and FIFO access on Xilinx-Virtex6 FPGA chip.