Four-bit absolute-value detector design and optimization

The advancement of neural prosthetics and neuroscience research has promoted the development of spike sorting. As an important part of spike sorting algorithms, people are interested in designing and optimizing a high-performance absolute-value detector with low delay and low energy consumption to adapt to and meet the requirements of hardware with accuracy and protection of related tissue. The paper aims to design a four-bit Absolute-Value Detector by using CMOS circuit and calculate the minimum delay of critical path and total energy consumption by using the Logic Effort Theory. In this way, a 51.8 FO4(1V) and 70.1 Eu(1V) detector could be achieved. Further discussion is needed to explore the individual effects of sizing and VDD scaling on delay and energy consumption. Ultimately, calculations should be conducted to determine the energy consumption at 1.5 times the minimum delay when both sizing and VDD scaling are applied to seek optimization. A 77.7 FO4 and 37.7 Eu Absolute-Value Detector is achieved finally. In conclusion, by designing a four-bit Absolute-Value Detector, this paper provides the fundamental ideas and methods for designing and optimizing multi-bit absolute-value detector.