Interface Trap Characterization in Junctionless Forksheet FET at Sub-3 nm Technology Node: A Reliability Assessment on Digital, Analog/RF, and Circuit Applications

In the recent times, the Forksheet (FS) FET has evolved as a potential candidature for next generation applications due the seamless integration of nFET and pFET with minimal n-p spacing. However, one of the serious concerns that bothers the reliability of devices is the presence of interface traps. Therefore, in this manuscript, for the first time, we aim to analyse the presence of acceptor and donor interface trap charges (ITCs) in sub - 3nm technology node for the Junctionless (JL) FSFET with well calibrated TCAD setup for digital, analog/RF, and circuit applications. Results demonstrated that the presence of acceptor ITCs in nFET and donor ITCs in pFET in the JL-FSFET device improves the overall digital performance of the device with switching ratio <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 10{^{{10}}}$ </tex-math></inline-formula> when compared to no trap scenario. At lower VGS, the presence of ITCs significantly impacted the analog/RF performance whereas increasing the VGS after a certain point overpowered the trap effects producing invariant changes in analog/RF performance indicating that the designed JL-FSFET is reliable and robust. Further, increasing the trap concentration from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 10{^{{12}}}~{\mathrm { cm}}^{-2}$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times 10{^{{12}}}~{\mathrm { cm}}^{-2}$ </tex-math></inline-formula> reduced the leakage currents in four orders and improved the switching ratio by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 10{^{{12}}}$ </tex-math></inline-formula> especially with the presence of acceptor ITCs in nFET and donor ITCs in pFET. Moreover, increasing the trap concentration at higher VGS, produced equal analog/RF performance with that of absence of traps making the device more reliable even with higher concentrations. The CMOS inverter layout for the JL-FSFET is designed with the presence and absence of ITCs and found that the ITCs based inverter produces near equal gain to that of no traps. Overall, this research paves a way towards the reliable performance of JL-FSFET in the presence of ITCs to be adopted into next generation digital, analog/RF IC applications.