A Hybrid RO-TDL-Based On-Chip Voltage Monitor for FPGA Applications

In recent years, field-programmable gate arrays (FPGAs) have become critical computing resources, featuring higher levels of system integration and accelerated clocking speeds. FPGA-based systems face increasing challenges in maintaining power and signal integrity. Consequently, a flexible and efficient power supply monitor is essential for evaluating the system’s performance and reliability. We propose an integrated power monitoring scheme within an FPGA, enabling real-time evaluation of power supply signal integrity. The monitor employs a hybrid structure combining a ring oscillator (RO)-based monitor and a tapped delay line (TDL)-based monitor, featuring first-order noise shaping and explicit dynamic-element matching (DEM) in its quantization. We analyze the principle of operation of the hybrid monitor and present its implementation in FPGAs. Demonstrated in an AMD Kintex-7 FPGA, tests show a voltage resolution of at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$12.96~\mu $ </tex-math></inline-formula>V and a precision of 8.03-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>V rms, and the effective bandwidth (BW) of the monitor is 10 MHz. The monitor utilizes only conventional logic resources and is delivered as a soft logic core. It can be migrated to different FPGA platforms and custom-integrated circuits with greater flexibility and integration.