A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline
Efficient binary polynomial multiplication (BPM) implementations are crucial for the practical deployment of bit flipping key encapsulation (BIKE) postquantum cryptography (PQC) due to its computation-intensive nature. To speed up BPM, this brief proposes a scalable and efficient architecture. The proposed architecture employs a novel blockwise sparsity algorithm, which segments sparse polynomials into blocks and leverages interblock and inner block sparsity to eliminate invalid computations, thereby significantly reducing computational operations. Moreover, a scalable block-by-block pipeline structure, along with a multibank random access memory (RAM) for sparse polynomials, is designed to effectively process blocks, resulting in substantial enhancement in performance. Experimental results on Xilinx Artix-7 Field-Programmable Gate Arrays (FPGAs) demonstrate significant performance superiority on the proposed architecture, compared with existing approaches. Across different bandwidth settings of 16, 32, 64, or 128, our design can achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.5\times \sim 35.1\times $ </tex-math></inline-formula>, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.9\times \sim 78.8\times $ </tex-math></inline-formula>, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.5\times \sim 112.7\times $ </tex-math></inline-formula>, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.5\times \sim 164.2\times $ </tex-math></inline-formula> speedup, respectively. Compared with state-of-the-art works, our design achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.8\times \sim 152.0\times $ </tex-math></inline-formula> improvements in area efficiency.
Authors
- Jia Hou (ORCID: https://orcid.org/0009-0007-1744-3667)
- Yishuo Meng (ORCID: https://orcid.org/0000-0002-3402-6386)
- Fahong Zhang (ORCID: https://orcid.org/0009-0008-8613-5323)
- Jianfei Wang (ORCID: https://orcid.org/0000-0003-0942-518X)
- Chen Yang (ORCID: https://orcid.org/0000-0002-8221-7670)
- Yang Su (ORCID: https://orcid.org/0000-0003-3619-7936)
Institutions
- Chinese People's Armed Police Force Engineering University (CN)
- Xi'an Jiaotong University (CN)
Publication Details
- Journal
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Published
- 2024-12-11
- DOI
- https://doi.org/10.1109/tvlsi.2024.3510541
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Key Research and Development Program of China