Design and simulation of parameter intensive shallow CNN acceleration method based on FPGA

Convolutional neural networks have become a key research object in computer vision related fields due to their powerful feature extraction and classification recognition capabilities. However, as CNN models continue to update and iterate, their structures become increasingly complex and the number of model parameters also increases. However, general CPUs cannot meet the large and intensive computing needs, and using GPUs has a series of problems such as high power consumption and noise. The cost of designing ASICs is too high, and they do not have the ability to update and iterate. With the rapid development of FPGA, the resources integrated on FPGA chips are constantly enriched, and some FPGA chips also integrate high-performance digital signal processing units. These advantages make FPGA an important platform for accelerating convolutional neural networks. This article focuses on the computational requirements of parameter intensive shallow CNN network models. By fully exploring their parallelism, structures such as convolutional layers with multiple convolution kernels in parallel, pooling layer pipeline and convolutional layer synchronization, and fully connected layer hierarchical computation are designed. Finally, it was deployed on the XCZU7EV-2FVC1156I chip of the Zynq UltraScale+MPSOCs EV series, and simulated using Vivado. The simulation data was validated against the results of external calculations to determine the logical and data correctness of the design. At the same time, compared with an accelerator design based on LeNet-5, this design has a shorter inference time for a single image at 86.68us and a computational performance of 19.96GOP/s under higher computational requirements, fully verifying the performance advantages of this design.