Unlocking Modern VLSI Placement with Cutting-Edge GPU Acceleration Integrated with Deep Learning Tool Kit

Objectives: In VLSI, cell placement is critical in determining the overall performance, area, runtime efficiency, and power consumption of integrated circuits. The objective of this work is to find the best possible locations for the cells to meet the mentioned constraints. Methods: The proposed method utilizes a deep reinforcement learning strategy with heuristics to address the complexities of modern VLSI design challenges. A multi-objective deep reinforcement learning approach fused with GPU acceleration is explored to optimize placement metrics like wirelength, congestion, and runtime to gain a globally optimal placement solution. The suggested method dynamically selects appropriate parameters, a process known as Parameter Tuning, to produce high-quality placement solutions. The strategy's potency is demonstrated using open-source benchmarks sourced from storage, with BlackParrot and MemPool. Findings: The trial outcomes of the strategy on benchmark data show considerable improvements in placement quality. It reduces wire length by up to 4% and congestion by about 10%. Moreover, it is highly scalable and reliable in providing global placement solutions. The reduced aspect ratio indicates lower chip area utilization and reduced power consumption. Novelty: The integration of GPU acceleration and deep learning methodology as a strategy for VLSI global placement has not been reported in prior placement work; however, similar approaches are available for legalization and detailed placement. Keywords: Placement, VLSI, Deep Learning, GPU Acceleration, Parameter Tuning