Fast layout pattern matching using spatial indexing

As technology nodes shrink and layout sizes grow, layout pattern matching in lithography defect detection becomes increasingly time-consuming. To address this, we propose a fast layout pattern matching algorithm based on spatial indexing. The method first uses geometric information to locate potential matching regions, then employs spatial indexing to divide the layout into sub-regions, quickly excluding irrelevant areas and improving efficiency. Multithreading and compiler optimizations further enhance speed. Experiments show that our approach achieves a 20- 30x speedup over commercial tools while maintaining 100% accuracy, demonstrating its effectiveness for very large-scale integrated circuit defect detection.