Accurate SEM contour-based measurement and analysis of SRAM patterns for enhanced design optimization

The critical dimension scanning electron microscope (CDSEM) plays an essential role in measuring sub-nanometer scale patterns after lithography and etching process. However, its measurement capabilities are limited, making it difficult to accurately measure complex pattern such as tip-to-tip or tip to side structures. Additionally, it’s very challenging for CDSEM to perform an accurate multiple-layer multiple-process data measurement and process characterization, such as etch bias and channel length/width uniformity. This paper addresses these challenges by performing SEM contours extraction and data analysis on the gate (GT) and active area (AA) stacking structures of Static Random Access Memory (SRAM) bit cell pattern. Utilizing SIEMENS EDA's Calibre SEMSuite and Calibre OPCVerify tools, we extracted contours from SEM images to analyze process variations at the center, middle, and edge positions of the wafer. By overlaying the contours of ADI and AEI, we determined the etch bias across the entire SRAM bit cell pattern. Additionally, by overlaying the contours of AA and GT, we ascertain the channel width and length (W/L) value of the transistors. This data provides a direction for optimizing SRAM layout design and establishes a systematic method for silicon data analysis.