The application of multiple patterning solutions based on process window analysis in lithography

Process miniaturization is a commonly used method in semiconductor manufacturing to achieve higher device density and better device performance at a lower cost. However, with the continuous improvement of process nodes, traditional pattern transfer methods face dual challenges of accuracy and cost. How to achieve accurate pattern transfer is a problem that the industry is facing and urgently needs to solve. This article proposes an innovative process window analysis (PWA) method for optimizing multiple patterning technology (DPT) to improve the success rate of pattern transfer and chip performance. By introducing process window analysis into the layout splitting process, this paper addresses the limitations of traditional judgment based on geometric proximity. This article takes the common odd circle topological graph in double patterning technology as an example, and demonstrates that through OPC (Optical Proximity Correction) optimization and simulated printing, the process window differences between different polygon pairs can be identified. By combining polygons with larger process windows into one group (mask) and splitting polygon pairs with smaller process windows into two masks. This can effectively split the layout and meet the requirements of printability. This method not only avoids the need for redesigning the circuit, but also achieves a design solution that can be immediately put into mass production. The experimental results demonstrate that the method proposed in this paper is an effective solution for layout splitting in DPT mode, providing a new technological approach for the semiconductor manufacturing field.