Rigorous simulation for impact of wafer topography on critical dimension

Due to integrated circuit evolution to lower technology node, the complexity of lithographic process is steadily increasing. Therefore, lithography simulation technology has become more essential as a tool to guide the design of lithography materials, tools and processes for semiconductor industry. In this paper, we use lithography software to run simulation in order to understand the 3D topography of actual wafer, lithography and the effects of development parameters on critical dimension. The result shows the trend of simulation contour CD on layer-A/B/C fits well with the SEM trend. The simulated profiles are also evaluated and compared with SEM images.