Silicon process characterization based on massive SEM contour extraction and hotspot pattern decomposition

As the production scale of HVM expands, the daily generation of measurement images and defect images increases significantly. Identifying the root causes of such a vast number of failure images remains a challenge. Insufficiently determined failure reasons and subsequent blind process modifications can be detrimental to mass-produced products. This article discusses extensive sampling and measurement of wafer samples, utilizing contour extraction and subsequent data analysis to identify numerous failure patterns that do not meet product requirements. By clustering these failure patterns, we can obtain overall distributions of similar patterns in terms of CD, EPE, etc. By integrating statistical methods with actual wafer processes, we present quantitative solutions for correcting these patterns. Using an iteratively developed new product as a case study, we show that pre-launch layout analysis, alongside the extensive measurement analysis previously discussed, results in a CD distribution and average yield that surpass those of earlier generation products. This validates the feasibility and reliability of our approach.