A methodology for random placement of unit patterns to identify potential design and process optimizations

The main hurdle in developing new IC technology nodes is the absence of high-quality, comprehensive layouts that can thoroughly test process capabilities, design and process interaction. In the initial stage of process development, it's necessary to define process specifications, specify OPC recipes, and establish design rules to confirm layout manufacturability. Each of these crucial tasks requires chip layouts to assess the quality, precision, and completeness of development outcomes. This paper primarily discusses how to utilize layout slicing to assemble a large layout. It involves cutting the hotspot-free design and contour layouts into slices of different sizes, enriching these slices through flipping, and then randomly assembling the enriched slices to form a large layout.