Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL

Hybrid PLLs (HPLLs) leverage the advantages of conventional analog and digital PLLs to cater to the high integration demand inherent with the advanced CMOS nodes, among which the charge-sharing (CS) integrator-based HPLL featuring ultra-compact area and ultra-low power consumption exhibits promising prospects. This work presents a comprehensive analysis concerning the CS integrator-based HPLL for the first time. The behavioral modeling is first conducted with a time-domain event-driven modeling method to simulate the piecewise-linear modulations on the oscillator frequency A noise model considering the slow-fast clock domain transitions and the digital-analog signal transitions inherent with the architecture is further proposed. The proposed models offer precise PN PSD estimations over the specified frequency range under all simulated conditions, whose integrated jitters differ by less than 5 fs compared with circuit simulations. The additional nonlinearity induced by the CS integrator is also considered, and an analytical prediction approach for the nonlinearity-induced spurs is presented, showing a capability of predicting the locations and amplitudes of the most significant spurious tones with a less than 4 % deviation in the relative offset frequency and a less than 5 dBc deviation in the relative amplitude.