A Collaborative Design of Broadband, High Linearity, and Flat Gain GaAs On-Chip Limiting LNA With Filtering Characteristic

In this paper, a broadband, high linearity, flat gain, limiting on-chip low noise amplifier (LNA) with filtering behavior is presented. In order to obtain the broadband impedance matching and low noise figure, the entire limiter is treated as the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pi $ </tex-math></inline-formula>-type equivalent input matching network of the LNA. Meanwhile, the RC energy storage network located at the transistor’s drain is employed to improve the input return loss. Adaptive bias networks and tapered topology are employed to ameliorate the linearity of the LNA. As the input power increases, the nonlinear behavior of the LNA is optimized by maintaining a stable gate bias voltage. A three-stage cascaded topology and an R-L-C feedback structure are employed to compensate for frequency-dependent losses, resulting in enhanced gain flatness of the LNA. The filtering characteristic is introduced by multiple transmission zeros through the DC bias circuit and parallel resonant branch. The measured results show that the proposed limiting LNA obtains a flat gain of 23 dB and a noise figure of 1.82 dB from 5-20 GHz with a rejection level greater than 38 dB. The output third-order intercept point of LNA reaches 20 dBm, while it can handle an input power of 40 dBm and occupies an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.4\times 0.9$ </tex-math></inline-formula> mm2.