Troubleshooting a High-Leakage Issue of an Overdrive FinFET ESD Power Clamp From Fabrication Perspective

This article presents the troubleshooting of a high-leakage issue in an overdrive fin field-effect transistor (FinFET) electrostatic discharge (ESD) power clamp. With silicon data exhibiting abnormal results, elaborate troubleshooting, including device reliability and simulation to silicon (S2S) gap analyses, are performed and presented. Through alignments of silicon data and presumptive simulation results, fabrication-induced root cause is successfully revealed. It is confirmed by physical failure analysis (PFA) results that the narrow width of high-resistance (HiR) resistors induces an aggressive pull-back effect during fabrication. This pull-back effect results in open connections of related HiR resistors and explains the observed abnormal silicon data.