Theoretical and Simulation-Based Investigation of Heat Transfer and Thermal Runaway in Power MOSFET Devices
Prediction of temperature rise in power MOSFET devices is of critical importance to ensure reliability and performance, and to prevent thermal runaway. While a safe operating area (SOA) is often prescribed for power MOSFET operation, experimentally determining the drain current limitation in the SOA to prevent thermal runaway is very cumbersome and often results in destruction of multiple devices tested to the limits. There remains a need for robust and accurate theoretical tools to predict the maximum allowable drain current in practical power MOSFETs. This work addresses this important need through analytical and numerical heat transfer modeling. Based on a simplifying assumption of 1-D heat flow in semi-infinite media surrounding the channel region, a Laplace transforms technique is used to derive an analytical solution for the transient temperature distribution in the device. Thermal runaway limits of the SOA are predicted by comparison of the predicted peak temperature with the maximum permissible temperature over the pulse duration. In addition, a numerical heat transfer simulation is developed for more general geometries, in which the 1-D heat flow assumption may not be valid. Results from both analytical model and numerical simulations are compared with manufacturer-specified SOA of several commercially available MOSFETs, showing good agreement in each case. This demonstrates the capability of the techniques developed here to predict the SOA without the need for cumbersome measurements. It is shown that the maximum temperature, and hence, the maximum allowable drain current does not depend on the channel width. The impact of the temperature coefficient of drain current on thermal performance is also investigated. The key novelty of this work is in developing two distinct techniques for thermal analysis of power MOSFETs, including thermal runaway prediction. This capability is a useful and practical alternative to cumbersome and destructive testing for predicting the SOA.
Authors
- A. Narasimhan (ORCID: https://orcid.org/0000-0002-0265-2147)
- R. A. Rao
- Ankur Jain (ORCID: https://orcid.org/0000-0001-5573-0674)
Institutions
- Analog Devices (United States) (US)
- The University of Texas at Arlington (US)
- Novel (United States) (US)
Publication Details
- Journal
- IEEE Transactions on Components Packaging and Manufacturing Technology
- Published
- 2024-12-11
- DOI
- https://doi.org/10.1109/tcpmt.2024.3515012
- Citations
- 2
- Primary Topic
- Silicon Carbide Semiconductor Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.42