To Develop Efficient Layout of CMOS Circuit for SRAM and Compare with Existing Technique to Show the Proposed Technique is Efficient

Different SRAM cell typologies includes 10T, 9T, 8T, and 7T in performance improvement and stability that enhances in specific regions as a trade-of. The count of the transistors have the possibility to be reduces to compensate certain area with the dynamic CMOS logic utilization that have the possibility in high performance maintenance. The current research focused on a novel sleepy technique along with AVS design is proposed for low-power SRAM for reducing power consumption utilizing multi-threshold CMOS circuit. Therefore, the SRAM us implemented in the research using sleep transistors along with an additional leakage current feedback-transistor along with MTCMOS primary structure which is implemented with an effective results in terms of certain factors such as delay, area, and power.