An All-Digital Dual-Mode Clock and Data Recovery Circuit for Human Body Communication Systems

This paper describes an all-digital clock and data recovery (CDR) circuit for implementing edge processing with a wireless body area network (WBAN). The CDR circuit performs delay-locked loop (DLL)-based and phase-locked loop (PLL)-based operations depending on the use of an external reference clock and is implemented using a digital method that is robust against external noise. The clock generator circuit shared by the two operation methods is described in detail, and the CDR circuit recovers 42 Mb/s input data and a 42 MHz clock, which are the specifications of human body communication (HBC). In DLL-based CDR operation, the clock generator operates as a digitally controlled delay line (DCDL) that delays the reference clock by more than one period. In PLL-based CDR operations, it operates as a digitally controlled oscillator (DCO) that oscillates the 42 MHz clock and adjusts the clock frequency. The proposed all-digital CDR is fabricated in 65 nm CMOS technology with an area of 0.091 mm2 and operates with a supply voltage of 1.0 V. Post-layout simulation results show that the lock time for DLL-based CDR operation is 1.6 μs, the clock peak-to-peak jitter is 0.38 ns, and the power consumption is 341.8 μW. For PLL-based CDR operations, the lock time is 6 μs, the clock peak-to-peak jitter is 2.92 ns, and the power consumption is 280.2 μW, respectively.