Fast Implementation of Eta-T pairing on FPGAs

Key distribution as a core feature of any security system is one of the challenging tasks in an online transaction. Pairing is used to share the key between the users as an answer to the underlying security problem. Diffie-Hellman key exchange protocol computes pairing in two rounds whereas Eta-T is the most efficient and widely used pairing algorithm in the field of elliptic curve cryptosystems. After careful analysis of existing Eta-T pairing techniques, this work proposes a modification from serial computation scheme to parallel for better overall performance. Parallel Karatsuba multiplier and Most Significant reduction algorithm is used to speed up and optimize the pairing algorithm. Consequently, proposed pairing accelerator calculates Eta-T pairing in just 36.4μs and takes only 3597 clock cycles with maximum clock frequency of 98.7 MHz on Virtex-II. Further, by increasing the number of coefficients processed per cycle up to 6, this work shows reduction in the calculation time and clock cycles of Eta-T pairing up to 26.16μs and 1997 respectively. It is also shown that calculation time starts increasing after reaching D = 14. Similarly, it is shown that the fastest calculation of Eta-T pairing in characteristics three over the field $F_3^{97}$ uses significantly less clock cycles than previous known implementations at the cost of less clock frequency.