Design and Prediction of Performance of Buffered Data Storage Systems for Non-Stationary Randomly Arriving Data [Thesis]

Problems related to the logical design of a buffered data storage system for non-stationary randomly arriving data are considered. A method consisting essentially of simulation using a digital computer has been developed to predict the performance of such a system for any given input distribution, and for various system parameters, and organizations. This method enables data losses to be predicted and their origin determined. The investigation was performed using input data and parameters which are expected from Columbia University's Nevis Synchrocyclotron Slow Neutron Velocity Spectrometer after contemplated improvements to the cyclotron are completed. The input data will have an arrival distribution characterized by a non-stationary Poisson distribution with rate, λ(t) = Kt^-1.2. The time interval of interest will extend from 20 to 3000 microseconds with respect to the cyclotron pulse. At t=20 microseconds the data arrival rate is expected to be 10⁷ events per second. Serial buffer systems were investigated in detail. Series-parallei systems were considered and compared. In particular a limiting case of series-parallel buffers called a "tree" was studied. It was shown that a conventional single level buffer could require over 700 words of 10 nanosecond memory to handle data rates of the type assumed if emptying of the buffer was not interlaced with its filling. If a Data Processing Unit is assumed which is capable of accepting data from the buffer system at a rate of up to one word every 700 nanoseconds then it is shown that a three level all serial buffer system requires only 7 words of 10 nanosecond memory and an additional 225 words of 50 nanosecond memory. Under the same conditions a "tree" organized buffer requires: 1 word of 10 nanosecond memory, 2 words of 20 nanosecond memory, 4 words of 40 nanosecond memory, and 228 words of 200 nanosecond memory. The tree organization, which requires the minimum number of the highest speed memory elements provides loss performance which is as good, or better than, the equivalent serially organized system. Other advantages of the tree organization are also indicated.