Research on the Implementation and Application of Improved Canny Algorithm for Image Edge Detection Based on FPGA

With the continuous development of digital image processing technology, edge detection technology is playing an increasingly important role in the field of image processing. The Canny algorithm is a classical gradient-based edge detection algorithm with excellent performance and robustness. However, due to its large computational amount and poor real-time performance, the traditional software implementation method has been unable to meet the demands of modern high-speed image processing. Therefore, the Canny algorithm hardware is turned into a popular research direction. As a programmable logic device, FPGA has the advantages of high flexibility, short development period and strong parallel computing power, which is widely used in the field of digital signal processing. At present, there has been a lot of research work on FPGA in implementing the Canny algorithm, but most of the schemes have some problems, such as slow speed and high resource occupancy rate. Therefore, this paper presents an improved scheme for the hardware design of Canny algorithm based on FPGA, aiming to improve the speed and efficiency of image processing while reducing the utilization of hardware resources.