Field-Programmable Gate Array-Based True Random Number Generator Using Capacitive Oscillators

In this paper, novel architecture of the true random number generator (TRNG) is presented. The proposed TRNG uses jitter in capacitive oscillators as a source of entropy. These capacitive oscillators exploit the input/output (I/O) buffers of a field-programmable gate array (FPGA) chip. A specific connection between these buffers allows cyclical charging and discharging of a parasitic capacitance associated with an external FPGA pin. If a few pins of an FPGA chip are not connected to any external components, they can be targeted to build the TRNG. The proposed TRNG requires only three external FPGA pins dedicated to capacitive oscillators, as well as 18 look-up tables (LUTs) and 20 flip-flops (FFs). Its throughput amounts to 11–13 Mbit/s. To pass all NIST SP800-22 statistical tests for a wide range of operating temperatures, the TRNG requires a post-processing circuit. The characteristic feature of the proposed TRNG is that it internally generates a signal indicating that a random bit was just produced. Therefore, no external clock signal is needed to sample the output.