R_ON Degradation Mechanisms of ON-Wafer 100-V p-GaN HEMTs Emulating Monolithically Integrated Half-Bridge Circuits

We present experimental data and numerical simulation results revealing different dynamic Rov mechanisms in on-wafer 100 V p-GaN HEMTs to be used as low- (LS) and high-side (HS) devices in monolithically integrated half-bridge circuits. A circuit configuration emulating stress conditions encountered by LS and HS devices was employed. Devices under test were subject to a total of 1000 -s OFF- and ON-state stress. The LS device degrades due to only OFF-state stress, while the HS device is further degraded by ON-state stress due to the finite voltage difference between source and substrate potentials. During OFF-state stress, dynamic Ron is caused by the hole emission of C-related acceptor traps in the buffer. The larger dynamic Ron observed during ON-state stress was attributed to the concurrent effect of back-gating from the substrate and hole emission from buffer traps, the latter being partially compensated by holes leaking into the device from the positively biased gate terminal.