A Novel Cost-Efficient Die-Level SiC MOSFET TDDB Testing Methods Based on Paralleling Wire Bonding

Silicon Carbide (SiC) MOSFETs are increasingly employed in power applications due to their superior performance characteristics compared to traditional silicon ($\mathrm{S i}$) devices. However, the SiC/SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> interface exhibits a higher electric field and a lower barrier height, which makes device breakdown more likely. To accurately and efficiently evaluate time-dependent dielectric breakdown (TDDB) of SiC MOSFET gates, this paper introduces a novel, cost-efficient m ethod f or c onducting simultaneous TDDB tests on MOSFET bare dies. Firstly, TDDB statistical models are reviewed to establish a reliability data analysis algorithm. To monitor the leakage current, which indicates MOSFET gate breakdown, a test circuit topology based on 32 parallel wire-bonded SiC MOSFETs is proposed, utilizing a Wilson current mirror and an operational amplifier. Following the circuit topology design, a TDDB testing hardware prototype is built, integrating stress application and a data acquisition board. A series of gate oxide reliability experiments are conducted on 1200V SiC MOSFET bare die samples, efficiently demonstrating a breakdown time of 34,030 seconds at $9 \mathrm{MV} / \mathrm{cm}$ and a life expectancy of up to 10 years.