Ageing and degradation study by thermal, electrical and radiation stress in SiC-JFET/Si-pMOS cascode switches

SiC transistors, particularly JFETs, due to their characteristics, can be an interesting solution for the development of current limiters in the space domain; however, the lack of previous results in this kind of application calls for a detailed study of their reliability. In this work, a test campaign is proposed and carried out to corroborate their correct operation and to detect potential problems. In this way, it will be possible to understand which are the most stressful conditions and what is its degradation process. High-temperature conduction tests and several electrical overload campaigns have been carried out on different transistor families and manufacturers. The results reveal, pending further conclusions, a promising future for this type of transistor technology for use in space current limiting applications.