Design of a low-power dynamic latched comparator for biomedical applications

Abstract The latched comparator is a fundamental component of all ADC topologies. Thermal noise, kickback noise, and offset voltage impact the energy efficiency of the comparator significantly. In cardiac IMD ADCs, latched comparator kickback noise may impact resolution, accuracy, and settling time. This paper describes the design and development of an a low-power dynamic latched comparator optimised for biomedical applications and running at 1V. The suggested comparator is achieved on a 45 nm CMOS technology node, having the main goal of reducing kickback noise. The main concept of the recommended comparator has been utilizing the novel resetting approach and kickback noise reduction approach to preserve the charge and kickback noise, respectively. This approach aids in minimizing delay, power consumption, and kickback noise using shared charging logic. The charging-sharing technique involves using a single-pass transistor positioned across two output nodes. The pass transistor distributes the charge evenly across two output nodes throughout the reset phase. Due to the shared charging of the load capacitances, the voltage at the output nodes would not drop under the threshold value. As a result, the input signal could be evaluated more quickly during the regenerative stage. The comparator’s delay is calculated using a rigorous statistical analysis considering the circuit’s random factors. The offset of the proposed comparator is verified using thorough Monte Carlo simulations. The comparator reduces power while preserving noise. Also, the measured simulation results of recommended comparator outperform state-of-the-art comparators regarding kickback noise, delay, power consumption, and power delay product (PDP). The input voltage inversely affects the comparator’s delay. Further, the simulation shows that the comparator consumes 9.36μW at 1 V and 1 GHz sampling frequency. The simulation results confirm that the suggested comparator effectively reduces power consumption by atleast 66.98%. The proposed comparator has less PDP value by 44.44%. Also, suggested comparator effectively reduces offset voltage by 7.6% but with a corresponding increase in the area by 5%. Additionally, the comparator successfully reduces kickback noise by 44.6%. The obtained results are not silicon proven and bound to be in the pre-silicon stage. The low-power behaviour of the suggested technique is validated using analytical derivations, PVT corner analysis, and post-layout simulation.