A 2 kHz, 34.1 nJ/Conv-Step 5.52-ENOB Asynchronous SAR ADC Using Pseudo N-Type Thin-Film Transistor
This paper presents a 6-bit asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) based on N-type Low-Temperature Polysilicon Thin-Film Transistor (LTPS-TFT). The design aims to provide a potentially cost-effective solution by only using N-type TFTs without compromising the ADC performance and die area. The ADC achieves 5.52-ENOB, 3.2 mW with a 2 kHz sampling rate, resulting in a figure of merit (FoM) of 34.1 nJ/conv-step.
Authors
- Mengzhe Liu
- Ting Zhou (ORCID: https://orcid.org/0000-0001-5887-3590)
- Jian Zhao (ORCID: https://orcid.org/0000-0003-2140-1236)
- Jiang Cheng (ORCID: https://orcid.org/0000-0002-0702-8087)
- Yongfu Li (ORCID: https://orcid.org/0000-0002-6322-8614)
- Yang Zhao (ORCID: https://orcid.org/0000-0001-8023-1551)
Institutions
- Shanghai Jiao Tong University (CN)
- Tsinghua University (CN)
Publication Details
- Published
- 2024-09-15
- DOI
- https://doi.org/10.1109/ifetc61155.2024.10771866
- Citations
- 1
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.21
Funders
- National Key Research and Development Program of China