An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC With Dual-Path Time-Assisted Residue Generation Scheme

This article presents a single-channel 10-bit pipelined analog-to-digital converter (ADC) with a dual-path time-assisted residue generation (TARG) technique running at 2.6 GS/s. A voltage-to-time converter (VTC) driving a current-integrating capacitor array through a time pulse facilitates the inter-stage residue amplification, which decouples the constraint between linearity and speed of the residue generation. The time residue path shortens the residue generation period with a lower linearity requirement and quantizes 4 bits simultaneously, speeding up the sub-stage ADC conversion; the voltage residue path achieves a dedicated inter-stage gain with high linearity and relaxed timing, suppressing noise of its subsequent stages. Furthermore, the inherent complementation characteristic of the voltage-time–voltage (V-T–V) conversion in the TARG scheme makes the prototype ADC intrinsically robust to process, voltage, and temperature (PVT) variations. Fabricated in a 28-nm CMOS process, the 2.6-GS/s pipelined ADC achieves a 51.4-dB signal-to-noise and distortion ratio (SNDR) and a 71.0-dB spurious-free dynamic range (SFDR) with a Nyquist input at a 0.9-V power supply, exhibiting a Walden figure-of-merit of 17.6 fJ/conversion-step. The SNDR varies by 1.25 and 1.55 dB across a supply variation of ±5% and a temperature range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${-} 40~{^{\circ }}$ </tex-math></inline-formula>C to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$85~{^{\circ }}$ </tex-math></inline-formula>C, respectively.