A Low-Noise Fractional-<i>N</i> Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC

This work presents a digital-to-time converter (DTC)-based fractional-N phase-locked loop (PLL) achieving low jitter and low spurs. Thanks to the proposed resistor-based inverse-constant-slope (R-ICS) DTC, the DTC random jitter is drastically reduced while retaining the excellent linearity performance of the conventional ICS-DTC architecture. Moreover, a tailored DTC range reduction technique is introduced to further improve DTC random noise. The PLL prototype has been fabricated in 28-nm CMOS and consumes 16.7 mW, with an active area of 0.21 mm2. It generates an output frequency in the 8.75–10.25-GHz range from a 125-MHz input reference frequency. At 9.25-GHz near-integer channels, it achieves a 67-fs rms jitter, a −108.5-dBc/Hz in-band phase noise (at 10-kHz offset), and fractional spurs below −63 dBc.