Taper-Angle-Induced Variation in n/p-Stacked Versus p/n-Stacked CFET

The complementary field-effect transistor (CFET), comprising vertically stacked gate-all-around field-effect transistor (GAAFETs), is a promising candidate to significantly enhance the layout area beyond GAAFETs. However, due to its more than double the height compared to GAAFETs, CFET is more susceptible to taper angle, resulting in notable performance disparities between p-type and n-type GAAFETs. Using 3-D technology computer-aided design (TCAD), we compare CFET to standard CMOS comprising GAAFETs from device performance variation perspective. Regarding taper angle, the top GAAFET in CFET exhibits minor degradation in subthreshold swing (SS) and drain-induced barrier lowering (DIBL), similar to GAAFETs in standard CMOS. In contrast, the bottom GAAFET in CFET shows substantial degradation, unlike standard CMOS and the top GAAFET in CFET. Therefore, since p-type and n-type GAAFETs are differently affected by taper angle depending on whether they are located at the top or the bottom in CFET, this article investigates the performance variations of inverter, NAND, and NOR gates based on the vertical positions of the GAAFETs. When n-type GAAFET is positioned at the bottom of CFET and taper angle increases to 4°, the inverter’s delay time varies by 2%p, dynamic power varies 5.6%p, and static power varies 73.4%p compared to when p-type GAAFET with poor performance is located at the bottom of CFET. Additionally, the two-input NAND and NOR gates showed more immunity to variations induced by taper angle when the n-type GAAFET is positioned at the bottom of CFET. This investigation led to the optimization of CFET structure to minimize performance variation.